A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs

Converting an HDL-based design into an emulation system for design veri cation is an extremely complex and time-consuming task. One possible solution to improve productivity is an e ective emulation-based design methodology that exploits the modularity of designs. This paper develops and explores such a methodology. We present a multi-level synthesis method which is able to establish a direct link between High-level Descriptive Language (HDL) constructs and corresponding circuit designs. This feature greatly facilitates HDL debugging capabilities such that when bugs are detected in subnetlists, links allow the corresponding HDL source code to be easily recognized. This powerful feature greatly reduces design debugging time. Experimental results on a set of industrial designs are reported in order to demonstrate the e ectiveness of the proposed synthesis methodology.